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| CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 - MARCH 2003 D D D D D D D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Buffered Inputs Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current - Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54AC32 . . . F PACKAGE CD74AC32 . . . E OR M PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y description/ordering information The 'AC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y + A * B or Y + A ) B in positive logic. TA PDIP - E -55C to 125C 55C SOIC - M ORDERING INFORMATION PACKAGE Tube Tube Tape and reel ORDERABLE PART NUMBER CD74AC32E CD74AC32M CD74AC32M96 TOP-SIDE MARKING CD74AC32E AC32M CDIP - F Tube CD54AC32F3A CD54AC32F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y H H L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 - MARCH 2003 logic diagram (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25C MIN VCC VIH Supply voltage High-level input voltage VCC = 1.5 V VCC = 3 V VCC = 5.5 V VCC = 1.5 V VIL VI VO IOH IOL t/v Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VCC = 1.5 V to 3 V VCC = 3.6 V to 5.5 V VCC = 3 V VCC = 5.5 V 0 0 1.5 1.2 2.1 3.85 0.3 0.9 1.65 VCC VCC -24 24 50 20 0 0 MAX 5.5 -55C to 125C MIN 1.5 1.2 2.1 3.85 0.3 0.9 1.65 VCC VCC -24 24 50 20 0 0 MAX 5.5 -40C to 85C MIN 1.5 1.2 2.1 3.85 0.3 0.9 1.65 VCC VCC -24 24 50 20 V V mA mA ns/V V V MAX 5.5 V UNIT NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 - MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.5 V IOH = -50 A VOH VI = VIH or VIL IOH = -4 mA IOH = -24 mA IOH = -50 mA IOH = -75 mA IOL = 50 A VOL VI = VIH or VIL IOL = 12 mA IOL = 24 mA IOL = 50 mA IOL = 75 mA II ICC Ci VI = VCC or GND VI = VCC or GND, IO = 0 3V 4.5 V 3V 4.5 V 5.5 V 5.5 V 1.5 V 3V 4.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.1 4 10 1 80 10 0.1 0.1 0.1 0.36 0.36 0.1 0.1 0.1 0.5 0.5 1.65 1.65 1 40 10 A A TA = 25C MIN 1.4 2.9 4.4 2.58 3.94 MAX -55C to 125C MIN 1.4 2.9 4.4 2.4 3.7 3.85 3.85 0.1 0.1 0.1 0.44 0.44 V MAX -40C to 85C MIN 1.4 2.9 4.4 2.48 3.8 V MAX UNIT pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85C and 75- transmission-line drive capability at 125C. switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) -55C to 125C MIN MAX 119 119 -40C to 85C MIN MAX 108 108 ns UNIT A or B Y switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) -55C to 125C MIN 3.3 3.3 MAX 13.3 13.3 -40C to 85C MIN 3.4 3.4 MAX 12.1 12.1 ns UNIT A or B Y POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 - MARCH 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) -55C to 125C MIN 2.4 2.4 MAX 9.5 9.5 -40C to 85C MIN 2.4 2.4 MAX 8.6 8.6 ns UNIT A or B Y operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd Power dissipation capacitance TYP 47 UNIT pF 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD54AC32, CD74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCHS343 - MARCH 2003 PARAMETER MEASUREMENT INFORMATION R1 = 500 S1 2 x VCC Open GND R2 = 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND From Output Under Test CL = 50 pF (see Note A) tw When VCC = 1.5 V, R1 = R2 = 1 k LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC 0V tsu Data 50% Input 10% 90% tr th 90% VCC 50% VCC 10% 0 V tf VCC Input 50% VCC 50% VCC 0V CLR Input VCC 50% VCC 0V trec VCC Reference Input CLK 50% VCC 0V VOLTAGE WAVEFORMS RECOVERY TIME VCC 50% VCC tPLH 50% VCC 0V tPHL 90% tr tPHL tPLH 50% VCC 10% tf 50% 10% 90% tr VOH VOL 90% VOH 50% VCC 10% VOL tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Input Output Control tPZL VCC 50% VCC 50% VCC 0V tPLZ 50% VCC tPZH VCC 20% VCC VOL tPHZ 50% VCC VOH 80% VCC 0 V In-Phase Output 50% 10% Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) Out-of-Phase Output 90% VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MECHANICAL DATA MCER002C - JANUARY 1995 - REVISED JUNE 1999 J (R-GDIP-T**) 14 LEADS SHOWN CERAMIC DUAL-IN-LINE PINS ** DIM A MAX B 14 8 A MIN 14 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22) 16 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22) 20 0.310 (7,87) 0.290 (7,37) 0.975 (24,77) 0.930 (23,62) 0.300 (7,62) 0.245 (6,22) B MAX C B MIN 1 0.065 (1,65) 0.045 (1,14) 7 C MAX C MIN 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 0-15 4040083/E 03/99 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002 N (R-PDIP-T**) 16 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE PINS ** DIM A 16 9 A MAX 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23,37) 0.850 (21,59) 20 1.060 (26,92) 0.940 (23,88) A MIN 0.260 (6,60) 0.240 (6,10) C MS-100 VARIATION AA BB AC AD 1 0.070 (1,78) 0.045 (1,14) D 8 0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.430 (10,92) MAX 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX A MIN 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated |
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